The present invention relates to an integrated circuit equipped with a redundant circuit, which redundant circuit is used in case there is any defective circuit. This invention also relates to a method of designing such an integrated circuit.
In recent years, along with the progress of high-level information technology, there has been a high demand for higher-speed and multifunctional semiconductor integrated circuits. At the same time, based on the distribution of mobile machines, a reduction in chip sizes of the semiconductor integrated circuits has also been demanded. Therefore, the semiconductor integrated circuits have continuously been provided in finer and higher-density structures. As the semiconductor integrated circuits become finer and in higher density, the process of manufacturing the semiconductor integrated circuits becomes more difficult, and the probabilities of the occurrence of defective products become higher. As conventional semiconductor integrated circuits that restrict the reduction in productivity due to the occurrence of defects, those semiconductor integrated circuits having spare redundant circuits for relieving defective circuits have been known.
FIG. 10 shows a schematic configuration of a conventional semiconductor integrated circuit. This semiconductor integrated circuit includes a core region 11 positioned at the center of the semiconductor integrated circuit, and an I/O region 12 positioned at the periphery of the semiconductor integrated circuit. Within the core region 11, there are disposed a functional circuit that achieves an actual operation function of the semiconductor integrated circuit, a redundant circuit that is used to replace a defective circuit within the functional circuit, a fuse box including fuses replacing the defective circuit with the redundant circuit, and a test circuit that carries out a test for detecting a defective circuit. An input buffer circuit and an output buffer circuit are disposed within the I/O region 12. The wiring between a cell, 14-1 and a cell 14-2 that constitute the functional circuit, for example, makes a detour around a fuse box 13 if the fuse box 13 is positioned on a shortest route between the two cells 14-1 and 14-2.
FIG. 11 is a flowchart showing a sequence of a method of designing a conventional semiconductor integrated circuit. FIG. 12 and FIG. 13 are for explaining the method of designing the conventional semiconductor integrated circuit. According to this method of designing the conventional semiconductor integrated circuit, at first, a user, who requests a maker for the manufacture of a semiconductor integrated circuit, designs a functional circuit 17 (step S11). Next, the maker carries out a timing verification of a case of disposing the functional circuit 17 between an input buffer circuit 15a and an output buffer circuit 16a (refer to FIG. 12) (step S12). The maker decides whether the timing is suitable or not (step S13).
When the maker decides that the timing is not suitable, the process is returned to step S11, that is, the user once more designs the functional circuit 17. On the other hand, when the maker decides that the timing is suitable, the maker, as the manufacturer of this semiconductor integrated circuit, designs a test circuit 18 (step S14). The maker then inserts a standard cell selector 19a into between the functional circuit 17 and the input buffer circuit 15a, and inserts a standard cell selector 20a into between the functional circuit 17 and the output buffer circuit 16a. Further, the maker provides the test circuit 18 between the standard cell selectors 19a and 20a in parallel with the functional circuit 17 (refer to FIG. 13).
Next, the maker verifies the timing of the test circuit 18 (step S15), and makes a decision as to whether the timing is suitable or not (S16). When the maker decides that the timing is not suitable, the process returns to step S14, that is, the maker once more designs the test circuit 18. On the other hand, when the maker decides that the timing is suitable, the maker verifies the timing of the functional circuit 17 in the state that the standard cell selectors 19a and 20a are inserted (step S17). Then, the maker decides whether the timing is suitable or not (step S18).
The reason why the maker verifies the timing of the functional circuit 17 again is as follows. Sometimes the functional circuit 17 does not operate normally because of a delay generated due to the insertion of the standard cell selectors 19a and 20a. When it is decided at step S18 that the timing is suitable, the maker finishes the design processing. On the other hand, when it is decided at step S18 that the timing is not suitable, the user redesigns the functional circuit (step S19), and the process returns to step S17.
For simplification of the explanation, only one input buffer circuit and one output buffer circuit are shown in FIG. 12 and FIG. 13. However, in reality, there are many input and output buffer circuits in the semiconductor circuit, and these input and output buffer circuits are connected to the functional circuit 17 and the test circuit 18 respectively. After the design of the semiconductor integrated circuit has been finished, the maker starts the manufacturing and shipment of the semiconductor integrated circuit. A test processing of the semiconductor integrated circuit carried out by the maker prior to the shipment of the semiconductor integrated circuit will be explained next. In the test processing of the semiconductor integrated circuit, an external testing apparatus not shown transmits a control signal for selecting the test circuit 18 side to the standard cell selectors 19a and 20a. Thus, the standard cell selectors 19a and 20a select the test circuit 18 side.
The external testing apparatus (not shown) transmits test data to the test circuit 18 through the input buffer circuit 15a and the standard cell selector 19a. The test circuit 18 receives this test data, and tests the functional circuit 17. Then, the test circuit 18 outputs a result of the test through the standard cell selector 20a and the output buffer circuit 16a. When a test result showing that there is a defective circuit in the functional circuit 17 has been output, the maker disconnects a fuse within the fuse box, and switches from the defective circuit to a redundant circuit, thereby replacing the defective circuit.
According to the above-described conventional technique, however, the fuse box 13 is disposed within the core region 11, and the fuse box 13 hinders the wiring within the core region 11. Therefore, there has been a problem that the efficiency of wiring within the core region 11 is lowered. Furthermore, after the user has designed the functional circuit 17, the maker verifies the timing, and then inserts the standard cell selectors 19a and 20a. Then, the maker verifies the timing of the functional circuit 17 again. When the timing is not suitable, the user designs the functional circuit 17 again. Therefore, there has been a problem that the efficiency of the design processing is lowered and that the cost increases.
It is one object of the present invention to provide an integrated circuit that improves the efficiency of the disposition and wiring within the core region, and a method of designing this integrated circuit. Further, it is an another object of the invention to provide an integrated circuit that lowers the cost of the integrated circuit by improving the efficiency of the design processing, and a method of designing this integrated circuit.
According to one aspect of the present invention, the integrated circuit comprises a functional circuit, a redundant circuit, and at least one input/output processing unit that carries out a signal transmission between the functional circuit and the outside. This input/output processing unit(s) incorporates a changeover unit which changes over from the defective circuit to the redundant circuit. Thus, the changeover unit is incorporated into the input/output processing unit(s). Accordingly, it is not necessary to dispose the changeover unit in the core region of the integrated circuit.
Further, according to another aspect of the present invention, the integrated circuit comprises a functional circuit, a redundant circuit, and a test circuit that carries out a test of detecting the defective circuit, at least one input buffer circuit, and at least one output buffer circuit. The functional circuit is provided between one of the output terminals of the input buffer circuit and one of the input terminals of the output buffer circuit, and the test circuit is provided between the other output terminal of the input buffer circuit and the other input terminal of the output buffer circuit. The input buffer circuit(s) inputs a signal from the outside, and outputs a signal from the two output terminals. The output buffer circuit(s) inputs a signal to a selective one of the two input terminals, and outputs a signal to the outside. Accordingly, it is not necessary to insert a selector between the input buffer circuit and the functional circuit and between the output buffer circuit and the functional circuit respectively.
Further, according to still another aspect of the present invention, the integrated circuit comprises a functional circuit, a redundant circuit, a test circuit, a plurality of bi-directional buffer circuits, and an output buffer circuit. The functional circuit is provided between one of the output terminals of the input buffer circuit of one bi-directional buffer circuit and one of the input terminals of the output buffer circuit of the other bi-directional buffer circuit, and the test circuit is provided between the other output terminal of the input buffer circuit of the one bi-directional buffer circuit and the other input terminal of the output buffer circuit of the other bi-directional buffer circuit. Accordingly, it is not necessary to insert a selector between each bi-directional buffer circuit and the functional circuit.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.